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cy7c131e, cy7c131ae cy7c136e, cy7c136ae 1 k / 2 k 8 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-64231 rev. *d revised june 15, 2012 1 k / 2 k 8 dual-port static ram features true dual-ported memory cells, which allow simultaneous reads of the same memory location 1 k / 2 k 8 organization 0.35 micron complementary metal oxide semiconductor (cmos) for optimum speed and power high speed access: 15 ns low operating power: i cc = 110 ma (typical), standby: i sb3 = 0.05 ma (typical) fully asynchronous operation automatic power-down busy output flag to indicate access to the same location by both ports int flag for port-to-port communication available in 52-pin plastic leaded chip carrier (plcc), 52-pin plastic quad flat package (pqfp) pb-free packages available functional description cy7c131e / cy7c131ae / cy7c136e / cy7c136ae are high-speed, low-power cmos 1 k / 2 k 8 dual-port static rams. two ports are provided permitting independent access to any location in memory. the cy7c131e / cy7c131ae / cy7c136e / cy7c136ae can be used as a standalone dual-port static ram. it is the solution to applications requiring shared or buffered data, such as cache memory for dsp, bit-slice, or multi- processor designs. each port has independent control pins; chip enable (ce ), write enable (r/w ), and output enable (oe ). two flags are provided on each port, busy and int . the busy flag signals that the port is trying to access the same lo cation, which is currently being accessed by the other port. the int is an interrupt flag indicating that data is placed in a unique location [1] . the busy and int flags are push pull outputs. an automatic power-down feature is controlled independently on each port by the chip enable (ce ) pins. the cy7c131e / cy7c131ae / cy7c136e / cy7c136ae are available in 52-pin pb-free plcc and 52-pin pb-free pqfp. r/ w l busy l ce l oe l a 9/10l a 0l a 0r a 9/10r r/ w r ce r oe r ce r oe r ce l oe l r/ w l r/ w r i/o 7l i/o 0l i/o 7r i/o 0r busy r int l int r arbitration logic (7c130/7c131 only) and interrupt logic control i/o control i/o memory array addr decoder addr decoder [2] [3] [3] logic block diagram 7c131e/7c131ae/ 7c136e/7c136ae arbitration logic interrupt logic [4] [4] [2] notes 1. unique location used by interrupt flag: 1 k 8: left port reads from 3fe, right port reads from 3ff; 2 k 8: left port read s from 7fe, right port reads from 7ff. 2. busy is a push-pull output. no pull-up resistor required. 3. int : push-pull output. no pull-up resistor required. 4. 1 k 8: a0?a9, 2 k 8: a0?a10, address lines are for both left and right ports.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 2 of 19 contents pin configurations ........................................................... 3 pin definitions .................................................................. 3 selection guide ................................................................ 3 maximum ratings............................................................. 4 operating range............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 ac test loads and waveforms ....................................... 5 switching characteristics ................................................ 6 switching characteristics ................................................ 8 switching waveforms .................................................... 10 ordering information ...................................................... 15 ordering code definitions ..... .................................... 15 package diagrams .......................................................... 16 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc solutions ......................................................... 19
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 3 of 19 pin configurations figure 1. pin diagram - 52-pin plcc (top view) figure 2. pin diagram - 52-pin pqfp (top view) 1 v cc oe r a 0r 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd oe busy int a nc/a10l r/w ce r/w busy int nc/a10r 0l l l l l l ce r r r r 7c131e/7c131ae 7c136e/7c136ae 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 16 17 18 19 20 21 22 23 24 25 26 52 51 49 48 47 45 44 43 42 41 40 v cc oe busy int a nc/a10l r/w ce r/w busy int nc/a10r 0l l l l l l ce r r r r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd 7c131e/7c131ae 7c136e/7c131ae [5] [5] [5] [5] 50 15 pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 9/10l [5] a 0r ?a 9/10r [5] address i/o 0l ?i/o 7l i/o 0r ?i/o 7r data bus input/output int l int r interrupt flag busy l busy r busy flag v cc power gnd ground selection guide parameter 7c131e-15 7c131ae-15 7c131e-25 7c136e-25 7c131e-55 7c136e-55 7c136ae-55 unit maximum access time 15 25 55 ns typical operating current 110 100 95 ma typical standby current for i sb1 (both ports ttl level) 50 45 45 ma typical standby current for i sb3 (both ports cmos level) 0.05 0.05 0.05 ma note 5. 1 k 8: a0?a9, 2 k 8: a0?a10, address lines are for both left and right ports.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 4 of 19 maximum ratings exceeding maximum ratings [6] may shorten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage to ground potential ..............?0.3 v to +7.0 v dc voltage applied to outputs in high z state .............................................?0.5 v to +7.0 v dc input voltage [8] .......................................?0.5 v to +7.0 v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >1100 v latch up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? ? c to +70 ? c 5 v 10% industrial ?40 ? c to +85 ? c 5 v 10% electrical characteristics over the operating range parameter description test conditions 7c131e-15 7c131ae-15 7c131e-25 7c136e-25 7c131e-55 7c136e-55 7c136ae-55 unit min typ [9] max min typ [9] max min typ [9] max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? ?2.4 ? ?2.4 ? v v ol output low voltage v cc = min, i ol = 4.0 ma ? ? 0.4 ? 0.4 ? ? 0.4 v v ih input high voltage 2.2 ? ?2.2 ? ?2.2 ? v v il input low voltage ? ? 0.8 ? 0.8 ? ? 0.8 v i oz output leakage current gnd < v o < v cc , output disabled ?20 ? +20 ?20 ? +20 ?20 ? +20 ? a i cc v cc operating supply current v cc = max, i out = 0 ma outputs disabled commercial industrial ? 110 115 190 200 ?100 110 170 180 ?95 105 160 170 ma i sb1 standby current, both ports, ttl inputs ce l and ce r > v ih , f = f max [7] commercial industrial ? 50 65 70 95 ?45 65 65 95 ?45 65 65 95 ma i sb2 standby current, one port, ttl inputs ce l or ce r > v ih , active port outputs open, f = f max [7] commercial industrial ? 120 135 180 205 ?110 135 160 205 ?110 135 160 205 ma i sb3 standby current, both ports, cmos inputs both ports ce l and ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 commercial industrial ? 0.05 0.05 0.5 0.5 ?0.05 0.05 0.5 0.5 ?0.05 0.05 0.5 0.5 ma i sb4 standby current, one port, cmos inputs one port ce l or ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, active port outputs open, f = f max [7] commercial industrial ? 110 125 160 175 ?100 125 140 175 ?100 125 140 175 ma notes 6. the voltage on any i/o pin cannot exceed the power pin during power-up. 7. at f = f max , address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using ac test waveforms input levels of gnd to 3 v. 8. pulse width < 20 ns. 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ.), t a = 25 c.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 5 of 19 capacitance [10] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 15 pf c out output capacitance 10 pf ac test loads and waveforms figure 3. ac test loads and waveforms (a) normal load (load 1) r1 = 893 ? 5 v output r2 = 347 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5 v output c= 5pf r th = 250 ? (used for t lz , t hz , t hzwe , and t lzwe including scope and jig) 3.0 v gnd 90% 90% 10% ? 5ns ? 5 ns (cy7c131e/cy7c131ae only) 10% all input pulses note 10. tested initially and after any design or proces s changes that may affect these parameters.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 6 of 19 switching characteristics over the operating range parameter [11] description 7c131e-15/7c131ae-15 7c131e-25/7c136e-25 unit min max min max read cycle t rc read cycle time 15 ?25?ns t aa address to data valid [12] ? 15?25ns t oha data hold from address change 3 ?3?ns t ace ce low to data valid [12] ? 15?25ns t doe oe low to data valid [12] ? 10?15ns t lzoe oe low to low z [13, 14, 15] 3 ?3?ns t hzoe oe high to high z [13, 14, 15] ? 10?15ns t lzce ce low to low z [13, 14, 15] 3 ?5?ns t hzce ce high to high z [13, 14, 15] ? 10?15ns t pu ce low to power-up [13] 0 ?0?ns t pd ce high to power-down [13] ? 15?25ns write cycle [16] t wc write cycle time 15 ?25?ns t sce ce low to write end 12 ?20?ns t aw address setup to write end 12 ?20?ns t ha address hold from write end 0 ?0?ns t sa address setup to write start 0 ?0?ns t pwe r/w pulse width 10 ?12?ns t sd data setup to write end 10 ?15?ns t hd data hold from write end 0 ?0?ns t hzwe [13] r/w low to high z [15] ? 10?15ns t lzwe [13] r/w high to low z [15] 3 ?3?ns notes 11. test conditions assume signal transition times of 5 ns or le ss, timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v and output loading of the specified i ol /i oh, and 30 pf load capacitance. 12. ac test conditions use v oh = 1.6 v and v ol = 1.4 v. 13. this parameter is guaranteed but not tested. 14. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 15. parameters t lzce , t lzwe , t hzoe , t lzoe , t hzce and t hzwe are tested with c l = 5 pf as in part (c) of figure 3 on page 5 . transition is measured 500 mv from steady state voltage. 16. the internal write time of the memory is defined by the overlap of ce low and r/w low. both signals must be low to initiate a write and either signal can terminate
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 7 of 19 busy/interrupt timing [17] t bla busy low from address match ? 15?20ns t bha busy high from address mismatch [18] ? 15?20ns t blc busy low from ce low ? 15?20ns t bhc busy high from ce high [18] ? 15?20ns t ps port setup for priority 5 ?5?ns t bdd busy high to valid data ? 15?25ns t ddd write data valid to read data valid [19] ? 25?30ns t wdd write pulse to data delay [19] ? 30?45ns interrupt timing t wins r/w to interrupt set time ? 15?25ns t eins ce to interrupt set time ? 15?25ns t ins address to interrupt set time ? 15?25ns t oinr oe to interrupt reset time [18] ? 15?25ns t einr ce to interrupt reset time [18] ? 15?25ns t inr address to interrupt reset time [18] ? 15?25ns switching characteristics (continued) over the operating range parameter [11] description 7c131e-15/7c131ae-15 7c131e-25/7c136e-25 unit min max min max notes 17. test conditions used are load 2. 18. these parameters are measured from the input signal ch anging, until the output pin goes to a high impedance state. 19. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address toggled. ce for port b is toggled.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 8 of 19 switching characteristics over the operating range parameter description 7c131e-55 7c136e-55 7c136ae-55 unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid [21] ?55ns t oha data hold from address change 3 ? ns t ace ce low to data valid [21] ?55ns t doe oe low to data valid [21] ?25ns t lzoe oe low to low z [21, 22, 23] 3?ns t hzoe oe high to high z [21, 22, 23] ?25ns t lzce ce low to low z [21, 22, 23] 5?ns t hzce ce high to high z [21, 22, 23] ?25ns t pu ce low to power-up [22] 0?ns t pd ce high to power-down [22] ?35ns write cycle t wc write cycle time 55 ? ns t sce ce low to write end 40 ? ns t aw address setup to write end 40 ? ns t ha address hold from write end 2 ? ns t sa address setup to write start 0 ? ns t pwe r/w pulse width 30 ? ns t sd data setup to write end 20 ? ns t hd data hold from write end 0 ? ns t hzwe r/w low to high z [24] ?25ns t lzwe r/w high to low z [24] 3?ns busy/interrupt timing [20] t bla busy low from address match ? 30 ns t bha busy high from address mismatch [25] ?30ns t blc busy low from ce low ? 30 ns t bhc busy high from ce high [25] ?30ns t ps port setup for priority 5 ? ns t bdd busy high to valid data ? 45 ns notes 20. test conditions used are load 2. 21. the internal write time of the memory is defined by the overlap of ce low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing sh ould be referenced to the rising edge of the signal that terminat es the write. 22. ac test conditions use v oh = 1.6 v and v ol = 1.4 v. 23. these parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 24. parameters t lzce , t lzwe , t hzoe , t lzoe , t hzce and t hzwe are tested with c = 5 pf as in part (b) of figure 3 on page 5 . transition is measured 500 mv from steady state voltage. 25. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address toggled.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 9 of 19 t ddd write data valid to read data valid [26] ?30ns t wdd write pulse to data delay [26] ?45ns interrupt timing t wins r/w to interrupt set time ? 45 ns t eins ce to interrupt set time ? 45 ns t ins address to interrupt set time ? 45 ns t oinr oe to interrupt reset time [27] ?45ns t einr ce to interrupt reset time [27] ?45ns t inr address to interrupt reset time [27] ?45ns switching characte ristics (continued) over the operating range parameter description 7c131e-55 7c136e-55 7c136ae-55 unit min max notes 26. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address toggled. ce for port b is toggled. r/w for port b is toggled during valid read. 27. these parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 10 of 19 switching waveforms figure 4. read cycle no. 1 [28, 29] figure 5. read cycle no. 2 [28, 30] figure 6. write cycle no. 1 (oe three-states data i/os ? either port) [31, 32] t rc t aa t oha data valid previous data valid data out addr either port addr access t ace t lzoe t doe t hzoe t hzce data valid data out ce oe t lzce t pu i cc i sb t pd either port ce /oe access t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha ce r/w addr t hzoe oe d out data in either port notes 28. r/w is high for read cycle. 29. device is continuously selected, ce = v il and oe = v il . 30. address valid prior to or coincident with ce transition low. 31. the internal write time of the memory is defined by the overlap of ce low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timi ng must be referenced to the rising edge of the signal that terminates the write. 32. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or t hzwe + t sd to allow the data i/o pins to enter high impedance and for data to be placed on the bus for the required t sd .
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 11 of 19 figure 7. write cycle no. 2 (r/w three-states data i/os ? either port) [33, 34] figure 8. read cycle no. 3 [35] switching waveforms (continued) t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance data valid t lzwe addr ce r/w data out data in [36] [37] t bha t bdd valid t ddd t wdd addr match addr match r/w r addr r d inr addr l busy l dout l t ps t bla read with busy t rc valid t hd t pwe notes 33. these parameters are measured from the input signal chang ing, until the output pin goes to a high impedance state. 34. if the ce low transition occurs simultaneously with or after the r/w low transition, the outputs remain in a high impedance state. 35. cel = cer = low. 36. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of tpwe or (thzwe + tsd) to allow the i/o drivers to turn off and data to be placed on the bus for the required tsd. if oe is high during a r/wn controlled write cycle, this requirements does not apply and the write pulse can be as short as the specified tpwe. 37. transition is measured 500 mv from steady state with a 5 pf l oad (including scope and jig). this parameter is sampled and n ot 100% tested.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 12 of 19 figure 9. busy timi ng diagram no. 1 (ce arbitration) [38] figure 10. busy timing diagram no. 2 (addr arbitration) [38] switching waveforms (continued) addr match t ps ce l valid first: t blc t bhc addr match t ps t blc t bhc addr l,r busy r ce l ce r busy l ce r ce l addr l,r ce r valid first: left addr valid first: addr match t ps addr l busy r addr mismatch t rc or t wc t bla t bha addr r addr match addr mismatch t ps addr l busy l t rc or t wc t bla t bha addr r right address valid first: note 38. if tps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 13 of 19 figure 11. interrupt timing diagrams switching waveforms (continued) write 3ff/7ff t ins t wc t eins t ha t sa t wins left side sets int r addr l r/w l ce l int r [39] [40] right side clears int r read 3ff/7ff t rc t einr t ha t inr t oinr addr r ce r r/w r int r oe r [40] [39] notes 39. parameter t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. 40. parameter t ha depends on which enable pin (ce l or r/w l ) is deasserted first.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 14 of 19 figure 12. interrupt timing diagrams switching waveforms (continued) write 3fe/7fe t ins t wc t eins t ha t sa t wins right side sets int l addr r r/w r ce r int l [41] [42] left side clears int l read 3fe/7fe t einr t ha t inr t oinr t rc addr r ce l r/w l int l oe l [41] [42] notes 41. parameter t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. 42. parameter t ha depends on which enable pin (ce l or r/w l ) is deasserted first.
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 15 of 19 ordering information speed (ns) ordering code package name package type operating range 1 k 8 dual-port sram 15 CY7C131AE-15JXI 51-85004 52-pin pb-free plastic leaded chip carrier industrial cy7c131e-15nxi 51-85042 52-pin pb-free plastic quad flatpack 25 cy7c131e-25jxc 51-85004 52-pin pb-free plastic leaded chip carrier commercial cy7c131e-25nxc 51-85042 52-pin pb-free plastic quad flatpack 55 cy7c131e-55jxc 51-85004 52-pin pb-free plastic leaded chip carrier commercial cy7c131e-55nxc 51-85042 52-pin pb-free plastic quad flatpack cy7c131e-55jxi 51-85004 52-pin pb-free plastic leaded chip carrier industrial cy7c131e-55nxi 51-85042 52-pin pb-free plastic quad flatpack 2 k 8 dual-port sram 25 cy7c136e-25jxc 51-85004 52-pin pb-free plastic leaded chip carrier commercial cy7c136e-25nxc 51-85042 52-pin pb-free plastic quad flatpack cy7c136e-25jxi 51-85004 52-pin pb-free plastic leaded chip carrier industrial 55 cy7c136e-55jxc 51-85004 52-pin pb-free plastic leaded chip carrier commercial cy7c136e-55nxc 51-85042 52-pin pb-free plastic quad flatpack cy7c136ae-55jxi 51-85004 52-pin pb-free plastic leaded chip carrier industrial cy7c136ae-55nxi 51-85042 52-pin pb-free plastic quad flatpack ordering code definitions temperature grade: x = i or c i = industrial; c = commercial pb-free package type: x = j or n j = 52-pin plcc; n = 52-pin pqfp speed grade: xx = 15 ns or 25 ns or 55 ns process version r4 = e x = a or blank part identifier: 13x = 131 or 136 technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy c 13x x - x x xx x e
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 16 of 19 package diagrams figure 13. 52-pin plcc (0.756 0.756 inches) j52 package outline, 51-85004 figure 14. 52-pin pqfp (10 10 2.0 mm) n5210 package outline, 51-85042 51-85004 *c 51-85042 *d
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 17 of 19 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable plcc plastic leaded chip carrier pqfp plastic quad flat package sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius a microampere ma milliampere mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c131e, cy7c131ae cy7c136e, cy7c136ae document number: 001-64231 rev. *d page 18 of 19 document history page document title: cy7c131e/cy7c131ae/cy7c136e/c y7c136ae, 1 k / 2 k 8 dual-port static ram document number: 001-64231 rev. ecn no. orig. of change submission date description of change ** 3038037 admu 09/24/2010 new data sheet *a 3394800 admu 10/04/2011 changed status from preliminary to final. updated maximum ratings (removed (pin 48 to pin 24)). updated electrical characteristics (changed minimum value of i oz parameter from ?10 a to ?20 a, changed maximum value of i oz parameter from +10 a to +20 a and changed maximum value of i sb3 from 0.5 ma to 15 ma for both commercial and industrial temperature ranges). updated package diagrams (updated revision of 51-85004 from *b to *c and revision of 51-85042 from *a to *c). updated in new template. *b 3403147 admu 10/12/2011 no technical updates. *c 3435230 admu 11/17/2011 updated features (removed a feature ?expandable data bus width to 16 bits or more using master/slave chip select when using more than one device.? and updated another feature to read as ?busy output flag to indicate access to the same location by both ports.?. updated functional description (updated the sentence in the first paragraph to read as ?the cy7c131e / cy7c131ae / cy7c136e / cy7c136ae can be used as a standalone dual-port static ram.?. updated note 2 to read as ?busy is a push-pull output. no pull-up resistor required.?. updated note 3 to read as ?interrupt: push-pull output. no pull-up resistor required.?. updated maximum ratings (removed ?(per mil-std-883, method 3015)?). updated electrical characteristics (removed the note ?see the last page of this specification for group a subgroup testing information.? and its reference in parameter column.). updated capacitance[10] (changed maximum value of c in parameter from 10 pf to 15 pf). updated ac test loads and waveforms . updated switching characteristics (removed the note ?see the last page of this specification for group a subgroup testing information.? and its reference in parameter column.). updated switching characteristics (changed the minimum value of t oha from 0 ns to 3 ns). removed the section ?typical dc and ac characteristics?. removed the section ?reference documents?. *d 3620277 admu 06/15/2012 added footnotes 9, 13, 17, 20, 36, 37, 39, 40, 41, and 42. missing overbars updated. removed ?slave diagrams?. updated figure 3 with value 5 ns. updated maximum ratings (updated static discharge voltage from 2001 v to 1100 v). corrected the typo in electrical characteristics . updated package diagrams (51-85042 from rev *c to *d). updated i cc parameters in electrical characteristics table. updated typical operating current parameters in selection guide .
document number: 001-64231 rev. *d revised june 15, 2012 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c131e, cy7c131ae cy7c136e, cy7c136ae ? cypress semiconductor corporation, 2010-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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